(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC). More particularly, it relates to a semiconductor IC including circuit elements for evaluating the characteristics of the ICs and having means for testing the evaluating circuit elements.
(2) Description of the Related Art
Semiconductor ICs are tested in several steps, such as after completion of the processes of forming ICs in a semiconductor wafer, after cutting IC chips away from the wafer, and after packaging the IC device. In the test after completion of the processes of forming the ICs in the wafer, in order to determine whether the wafer or the ICs in the wafer are usable or not, the characteristics of fundamental and typical circuit elements in the wafer, such as a resistor and a transistor, are tested and evaluated. Typical fundamental circuits, such as a flip-flop, an AND gate, also may be tested and evaluated. Normal circuits formed in each IC chip may be tested through bonding pads provided in each IC chip with a test facility (IC tester). However, the fundamental circuit elements cannot be directly tested because they have been already mutually-connected in the wafer to form desired ICs, and accordingly almost none of the terminals thereof appear on the surface of the wafer, and other terminals appearing on the surface are too small to allow direct contact with a test probe thereon.
Then, additional fundamental circuit elements, i.e., so-called monitor elements for testing and evaluating the characteristics of the wafer or the ICs in the wafer, are formed in a spare portion(s) of the wafer, in each IC chip, or as a special IC chip. The additional fundamental circuit elements are formed by the same processes used for the formation of the normal circuits, and accordingly, are regarded as circuit elements having the same characteristics as circuit elements in the normal circuits, and thus, the characteristics of the circuit elements in the normal circuits may be evaluated by testing and evaluating the additional circuit elements. When the additional circuit elements are formed in the spare portion of the wafer, although this may be beneficial for integration, an evaluation cannot be made of the validity of each IC chip and a test of the characteristic cannot be carried out after the IC chips are cut away from the wafer or after packaging. When the additional circuit elements are formed in each IC chip, it contributes to an improvement of the yield of the IC chips, because the evaluation and determination of the use may be effected for each IC chip.
The above problem of placing the test probe in contact with the terminals still remains unless the additional circuit elements are formed. When the additional circuit elements are formed in the spare portion in the wafer or as the special IC chip, bonding pads may be also formed around the additional circuit elements in a same way as for forming normal bonding pads, and thus these methods will easily solve the above problem. However, the former method involves the problems of a limitation of the validity of each IC chip and a limitation of the test after cutting the IC chips, as set forth above. The latter method also involves a problem of low availability of the IC chips in the wafer in addition to the above problems. When the additional circuit elements are formed in each IC chip, the problem in question may be greatly increased, because the size of the bonding pad necessitates the use of a considerably large area, for example, approximately several tens of micron-meters (.mu.m)=.times. several tens of micron-meters to approximately 100 .mu.m=100 .mu.m, to enable contact to be made by the test probe. Therefore, apparently, additional bonding pads each having a same size as the normal bonding pad cannot be actually provided, due to the restriction of the integration of the IC chip. The test of the additional circuit elements may be realized by using spare normal bonding pads which are not used for the normal circuits. However, in general, there are not enough spare normal bonding pads to allow testing of all of the additional circuit elements. Even if special bonding pads each having a considerably smaller area than that of the normal bonding pad are provided in each IC chip, a special test facility including a specially shaped test probe may be required. Moreover, the limitation of the tests after packaging the IC, etc., will still remain.